1. Field of the Invention
The present invention generally relates to the testing of very large-scale integrated circuits and, more particularly, to the testing of such circuits of the type known as application specific integrated circuits (ASICs).
2. State of the Art
In the semiconductor industry, it is commonplace to manufacture integrated circuits or "chips" which each comprise hundreds of thousands, if not millions, of individual circuit components such as transistors. Although testing of such integrated circuits can be a formidable task, it is usually economical to devise routine testing programs when the integrated circuits have a standardized design and are produced in large volumes.
In recent years, technology has developed to economically provide integrated circuits of the type known as application-specific integrated circuits (ASICs). In essence, ASIC chips are custom-designed circuits of the LSI (large scale integration) or VLSI (very large scale integration) class. ASIC chips often include one or more functional blocks which, individually, may be classified as an LSI or VLSI circuit. For instance, the functional blocks within an ASIC chip may comprise one or more random access memories (RAMs), read-only memories (ROMs), state machines, or programmable logic array (PLAs).
ASIC chips are normally characterized by relatively low production volumes. Thus, while ASIC chips and the functional blocks therein require testing to the same degree as standard-design integrated circuit chips, the low production volumes of ASIC chips usually imply that the testing techniques for standard-design chips cannot be used economically for ASIC chips. Moreover, the testing of functional blocks within ASIC chips can be quite complex when the ports of a block cannot be directly accessed from the pads of an ASIC chip. Such difficulties occur, for example, when a functional block is a component of a larger functional block which, itself, is one of many component circuits within a host ASIC chip.
Various methods have been proposed for testing functional blocks that are embedded within ASIC chips. Examples of such methods are discussed in the article "Logic Verification and Production Testing of Non-structured Embedded VLSI Blocks," Breitenwisher, T. G., Proceedings of the 1987 IEEE Custom Integrated Circuits Conference, pp. 62-65.
In practice, the implementation of test procedures for ASIC chips is at least partly manual because individual attention must be paid to isolating the functional blocks and to providing conductors within the chips to allow the functional blocks to be tested via signals which are input to the chip pads. According to conventional design practice, multiplexers often are embedded within ASIC chips for facilitating the testing of functional blocks via selected input/output pads on the chips. Typically, the proper placement and connections for such multiplexers requires the expenditure of substantial time by an experienced engineer.
To test an isolated functional block within an ASIC chip, it is also known to apply test mode vectors to the chip pads. Conceptually, a chip pad and the logic value on it can be thought of as an ordered pair. Therefore, a test mode vector can be defined according to a set of such ordered pairs, where the width of the vector equals the number of ordered pairs that it contains. One method for generating test mode vectors is described in an article by M. Arif Samad and T. Butzerin entitled "A Methodology for the Test of Embedded Compiled Cells," Proceedings of the 1988 IEEE Custom Integrated Circuits Conference, pp. 16.7.1-16.7.3.